As a new type of memory, a non-volatile memory (NVM) has many advantages, such as addressing by bytes, no data loss after power outrage, high storage density, no need for frequent refreshing, and low consumption. Therefore, the NVM is appropriate as a memory (or referred to as a main memory). However, the NVM also has some disadvantages, such as a relatively long write delay, and a limited write quantity. The NVM and an existing dynamic random access memory (DRAM) may jointly form a hybrid memory. Temporary data generated by an application program may be stored into the DRAM, and permanent data generated by an application program may be stored into the NVM.
In order to use the NVM as a memory, an existing system structure and software architecture need to be re-designed or optimized. In a feasible method, a software transactional memory (STM) technology is used. The technology can enable management of the NVM memory while maintaining transaction characteristics. The transaction characteristics include atomicity, consistency, isolation, and durability of a transaction. In addition, because the STM technology is based on an existing programming model, managing and controlling the NVM by using the STM technology is likely to be accepted and used by a programmer.
To ensure consistency during use of an NVM memory, a write request scheduling order needs to meet a linearizability requirement. That is, for a same transaction, a memory controller needs to first sequentially send a log write request and a commit write request of the transaction to the NVM memory, and then send a data write request of the transaction to the NVM memory, so as to perform an in-place update on data of the transaction.
In the STM technology, non-volatile heaps are created to manage the NVM memory, and write-ahead logging (WAL) may be used to ensure transaction consistency. Specifically, the non-volatile heaps need to send a memory barrier (or referred to as a persistent memory barrier) request to the memory controller between sending a log write request and sending a commit write request to the memory controller and between sending a commit write request and sending a data write request to the memory controller, so that in a write request queue in the memory controller, the log write request, the commit write request, and the data write request of the same transaction are separated by memory barriers. Therefore, in consideration of impact of memory barriers, when sending a write request to an NVM memory, the memory controller cannot concurrently send two write requests separated by a memory barrier to the NVM memory. Although this write request processing manner ensures transaction consistency, a relatively small quantity of write requests are processed concurrently due to existence of the memory barrier. Therefore, storage space of a memory is not fully used, and write requests are processed at low efficiency.